1. Field of the Invention
The present invention relates to a level shift circuit, and more particularly, to a level shift circuit without junction breakdown transistors.
2. Description of the Prior Art
The quality of a gate oxide of a metal oxide semiconductor (MOS) transistor affects the characteristics of the MOS. For example, a charge disposition variation of the gate oxide of a transistor will change a threshold voltage Vt of the transistor. Moreover, the existing charge in the gate oxide also reduces a breakdown voltage of the transistor. Please refer to FIG. 1, which is a schematic diagram of a charge disposition of a prior art MOS transistor 10. The MOS transistor 10 comprises a metal layer (which serves as a gate electrode) 11, an oxide layer 12, and a substrate 13. In general, charges existing in the oxide layer 12 of a transistor are divided into four categories: interface trapped charges (Qit) 14, fixed oxide charges (Qf) 16, oxide trapped charges (Qot) 18, and mobile charges (Qm) 20. Most interface trapped charges 14 form at an intersection between the oxide layer 12 and the substrate 13, where a disposition of lattices is discontinuous. The discontinuity makes silicon-silicon bonds of the silicon atoms in the substrate 13 and silicon-oxide bonds of the Silica in the oxide layer 12 to break, consequently generating the interface trapped charges 14. Most fixed oxide charges 16 are disposed at an intersection between the oxide layer 12 and the substrate 13. The fixed oxide charges 16 are positive and will not disappear by a discharging process. The oxide trapped charges 18 are disposed evenly in the oxide layer 12 and exist because of defects of the oxide layer 12. The mobile charges 20 are mainly sodium ions and potassium ions, which are introduced in a MOS transistor manufacturing process and move freely within the oxide layer 12.
Please refer to FIG. 2, which is a schematic diagram of a structure of the MOS transistor 10 shown in FIG. 1. The MOS transistor 10 comprises an n-type metal oxide semiconductor (NMOS) transistor 22 and a p-type metal oxide semiconductor (PMOS) transistor 24. The NMOS transistor 22 comprises a metal gate electrode 26, an n-doped source electrode 28, an n-doped drain electrode 30, and an oxide layer 31. The PMOS transistor 24 comprises a metal gate electrode 32, a p-doped source electrode 34, a p-doped drain electrode 36, and an oxide layer 37. Both the NMOS transistor 22 and the PMOS transistor 24 are formed on a p-substrate 38.
The PMOS transistor 24 further comprises an n-well 40 disposed next to the p-substrate 38 for isolating the source electrode 34 and the drain electrode 36 of the PMOS transistor 24 from the p-substrate 38. The n-well 40 also serves as a current channel when the PMOS transistor 24 actuates.
For the NMOS transistor 22, if a voltage difference between the gate electrode 26 and the drain electrode 30 is greater than a predetermined threshold value, an external electric field appears and destroys the covalence bonds in molecules in the NMOS transistor 22. Because the oxide layer 31 contains a plurality of charges, if the external electric field changes, the number of electrons in the oxide layer 31 increases abruptly, making the oxide layer 31 breakdown and the NMOS transistor 22 invalid. Similarly, if a voltage difference between the gate electrode 32 and the drain electrode 36 of the PMOS transistor 24 is greater than a predetermined threshold value, another external electric field appears and destroys the covalence bonds in molecules in the PMOS transistor 24. Because the oxide layer 37 comprises a plurality of charges, if the external electric field changes, the PMOS transistor 24 will be also invalid.
Please refer to FIG. 3, which is a schematic diagram of a level shift circuit 50 according to a prior art. The level shift circuit 50 comprises two PMOS transistors 52, 56 and two NMOS transistors 54, 58. A gate electrode of the transistor 54 is connected to a voltage source Vdd. A source electrode of the transistor 52 and a source electrode of the transistor 56 are connected to a voltage source Vn. An input voltage Vin ranges between a voltage level of the voltage source Vdd (high voltage level) and that of ground (low voltage level, zero volts).
For example, if the voltage source Vn is 10 volts and the voltage source Vdd is 3.3 volts, the breakdown voltage level of each of the transistors 52, 54, 56, and 58 is 10 volts, and the input voltage Vin is at the high voltage level, the transistor 58 actuates and the transistor 54 does not actuate. Because the transistor 58 is actuated, the voltage level at a node B approaches zero, which actuates the transistor 52 and makes the voltage level at a node A approach 10 volts. The high voltage level at the node A will not actuate the transistor 56, so the output voltage Vout of the level shift circuit 50 approaches zero. Although the transistors 52, 58 are actuated, a reverse voltage across the drain electrodes and the gate electrodes of both the transistors 52, 58 approaches 10 volts, which results in a number of breakdown currents appearing in a corresponding oxide layer, destroying the level shift circuit 50.
On the other hand, if the input voltage Vin is at the low voltage level, the transistor 58 does not actuate and the transistor 54 actuates, which makes the voltage level at the node A approach zero. The low voltage level at the node A actuates the transistor 56. The actuated transistor 56 makes the voltage level at the node B approach 10 volts, which will not actuate the transistor 52 and consequently the output voltage of the level shift circuit 50 approaches 10 volts. Although the transistors 54, 56 are actuated, a reverse voltage across the drain electrodes and the gate electrodes of the transistors 54, 56 still approaches 10 volts, which results in a number of breakdown currents appearing in a corresponding oxide layer destroying the level shift circuit 50.
To prevent the transistors 52, 54, 56, and 58 from breaking down, the level shift circuit 50 has to control the voltage level of the voltage source Vn to guarantee that the four transistors 52, 54, 56, and 58 function normally.
As described previously, because the transistors 52, 54, 56, and 58 are conventional MOS transistors, that is, the transistors 52, 54, 56, and 58 have a low breakdown voltage resulting from a charge doping existing in the oxide layer, the transistors 52, 54, 56, and 58 are unstable when the voltage level of the voltage source Vn becomes high. Therefore, the prior art level shift circuit 50 is not capable of transferring a voltage with a low voltage level to a voltage with a very high voltage level.
It is therefore a primary objective of the claimed invention to provide a level shift circuit, whose breakdown voltage is high, to solve the above-mentioned problem.
According to the claimed invention, the level shift circuit includes at least a complementary metal oxide semiconductor (CMOS) transistor formed on a p-substrate. The CMOS transistor has a PMOS transistor and an NMOS transistor, which includes a gate electrode, a drain electrode having an n-well formed on the p-substrate and a first N-doped region formed inside the n-well, and a source electrode having a second N-doped region formed on the p-substrate.
It is an advantage of the claimed invention that level shift circuits provided with a claimed NMOS are capable of enduring a high breakdown voltage. Additionally, forming an n-well in an NMOS is not complicated and can be performed in an ordinary NMOS-manufacturing process.